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ATmega128
Timer/Counter
Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
– TIFR
Read/ W rite
Initial Value
OCF2
R/ W
0
TOV2
R/ W
0
ICF1
R/ W
0
OCF1A
R/ W
0
OCF1B
R/ W
0
TOV1
R/ W
0
OCF0
R/ W
0
TOV0
R/ W
0
TIFR
? Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. W hen the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
? Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. W hen the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Inter-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
P W M mode, this bit is set when Timer/Counter2 changes counting direction at $00.
159
2467X–AVR–06/11
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